1. Field of the Invention
The present invention is related to a storage device and a data process method, and more particularly to a non-volatile storage device and corresponding data process method.
2. Description of the Related Art
There are many types of memory used in the storage device and the Flash Memory is one of the mainstream products in the market. As a non-volatile memory, the Flash Memory, compared to the traditional hard disk, is power-save, low-weight, shock-proof, low working temperature, quiet, and high storage speed. In some portable electrical devices, the flash memory has been replaced the traditional hard disk.
The flash memory can be sorted into Single Level per Cell (SLC) and Multiple Level per Cell (MLC). Each memory cell in the memory cell array of SLC can record one bit data by performing charge/discharge procedure. The voltage distribution of the memory cells on the SLC memory is shown in FIG. 1. There are two voltage states after discharging of the memory cell on the SLC memory. The voltage state in the left side of the reference voltage shows the discharged, memory cells distribution, which usually denotes logic data “1”. The voltage state in the right side of the reference voltage shows the charged, memory cells distribution, which usually denotes logic data “0”.
On the other hand, each memory cell in the MLC memory array can record more than one bit data. Referring to FIG. 2, the charged/discharged, two bits memory cells distributions on the MLC memory array of the different voltages are shown. It can be sorted to four voltage states, after charging/discharging of the two bits memory cells on the MLC memory array, each of which denotes different logic data. The four voltage states can be separated by three reference voltage Vr1, Vr2, Vr3. If the voltage is less than Vr1, which is located at the leftmost side, corresponding memory cells denote logic data “11”. If the voltage is between Vr1 and Vr2, the memory cells denote logic data “10”. If the voltage is between Vr2 and Vr3, the memory cells denote logic data “00”. If the voltage is more than Vr3, the memory cells denote logic data “01”. Understandably, the above introduction of the encoder mode is only an example. The logic data denoted by the voltage state can be different according to different encoder modes of the voltages of the non-volatile storage memory.
As shown in FIGS. 1 and 2, even in the same MLC memory cell, there are a plurality of voltage states. The differences between the voltages in different voltage states are closer than that of the SLC memory cells. Referring to FIG. 2, the two voltages are close, one of which is the highest voltage of the voltage state denoting logic data “11” and other one of which is the lowest voltage of the voltage state denoting logic data “10”. Consequently, an original voltage state maybe drift to another non-objective voltage state because the MLC memory cell is subject to leakage of storage charges or influences of read/write disturb. In this case, the correctness of the data stored in the two bits MLC flash memory is affected. It will be even worse when there are eight voltage states in one memory cell of a three bits MLC flash memory. As shown in FIG. 2, the memory cell at the leftmost side is easiest to be affected by the neighbored charged, memory cells and results to voltage state's drift.
In order to maintain the accuracy of the input/output data in the flash memory, Error Correction Code (ECC) is usually employed to protect the data. However, during outputting the data, if the data include wrong bits, it would need more time to recover it. That is, if the data read from the flash memory include the wrong bits, it takes ECC a long time to perform recovering procedure. Especially, the more bits are protected by the ECC, the more time is required in the recovering procedure. The read/write time is affected.
With the reduction of the MLC flash memory processing and increasing of numbers of voltage states included in the memory cell, the charges-storage capability of the memory cell is worse, which thereby result in errors in data storage. Subsequently, the high capability of ECC is needed. At the same time, more bits are needed in every length unit protected by ECC. Generally, the redundancy bits of the flash memory are used for storage some managing data. If the redundancy bits are occupied, the storage space of the managing data will be reduced and then may result in lower of managing design flexibility.
Hence, it is desired to provide a storage device with improved read/write speed and accuracy of data and corresponding data process method to solve the above-described problems.